If N3B started volume manufacturing late 2022 why hasn't wasn't any product announced yet? Are all the N3B production lines idle and bleeding money?Reply
I don't think they are idle at this point. They are working overtime but the yields are bad. They were likely idle in 2022, however. Why does TSMC say they started volume manufacturing of N3B in 2022? Because TSMC is always on schedule, even when they are a year late. Firstly, the only reason N3E exists is because the original N3 which they are calling N3B, didn't turn out as intended. As far as I know, only Apple is going to use it, later than they would have wanted, and only for the ultra high end of their product lineup. Rumor has it that TSMC is currently having trouble keeping up with Apple's demand for N3B even for the reduced A17 order. They are producing on it, it's just slow going. Perhaps one could say N3B was around to be available for "volume manufacturing" since late 2022 if one only wanted a small volume and was willing to pay a lot for it. N3B seems like a dead end with N3E set to replace it, supposedly with HVM in H2 2023. TSMC promised N3E HVM would begin 1 year after N3B HVM, and since apparently TSMC always keeps their promises we can't really trust that the H2 2023 situation for N3E will be any better than what the H2 2022 situation for N3B was, even though by now TSMC knows if anyone will actually be producing anything on the supposedly volume-ready node in H2 2023.Reply
What happens while they are still working on yields? Do the use a reduced number of EUV machines and reallocate them to production lines of active nodes or do all the many N3B EUV machines stay idle in the N3B fab?Reply
Just to avoid confusion, I want to stress that they don't directly need less machines because of bad yields. Bad yields means they need more capacity for the same number of good chips. But since Apple most likely originally intended to use N3B for the entire iPhone 15 lineup, they are likely looking at a reduced capacity demand for N3B.
But to answer your question, I don't know. My guess would be they didn't have much idle for that long. They never built out the originally intended capacity for N3B because before it became necessary for them to do so they made the necessary decisions with their customers regarding intended usage of the node. TSMC are very good at managing their capacity. In the foundry business that's key to profitability.Reply
If current rumors are to be believed, Samsung’s 3GAP outperforms N3 and N3E on the latest PDK. The only question now is the yield. I suspect N3E and 3GAP are in the 50% range. 30% for N3.
I don’t think TSMC’s domination is a certainty at this moment, and I believe warren buffet’s decision to dump TSMC has less to do with China risks (Why didn’t he sell AAPL if China was a major risk) and more to do with Samsung.Reply
Using the Apple A9 processor and Nvidia Pascal GPUs, we can estimate the performance-per-watt gap between Samsung's 14LPP and TSMC's 16FF+. I estimate the gap between the 2 to be at 1.3-1.35x, so I'll be using 1.32x for my calculations.
The 1.32x figure can be demonstrated to be close to reality by comparing Nvidia's Ampere graphics cards to their Turing predecessors. By isolating the GPU core power, adjusting for frequency, and assuming a n% increase in transistors is a n% increase in power and no efficiency improvements from the Ampere architecture alone, we can determine Ampere to be 26.3% more efficient than Turing. Theoretically, 12FF to 8LPP would be a gain in 27.3% in efficiency. The power adjustment for frequency is based on the formula of f^3.33, wherein a 10% increase in frequency results in an increase in power of 37.4%. This is because the formula for dynamic power is power = cfv^2 (f is frequency and v is voltage) and voltage scaling isn't typically linear with frequency, but slightly above it. The f^3.33 is surprisingly accurate with a wide range of processors as long as they aren't falling off a voltage-frequency cliff.
16FF+ -> N7 is a gap of 2.5x, N7 to N5 is a gap of 1.43x, and N5 to N4P is a gap of 1.28x. Altogether, 16FF+ to N4P is a gain of 4.59x efficiency or a reduction in power of 78.16%. 16FF+ to N3 would be 4.76-5.1x efficiency (a decrease in power of 79-80.4%). 16FF+ to N3E would be 5.25x efficiency or a reduction in power of 80.96%.
14LPP -> 10LPE is a gap of 1.43x, 10LPE -> 10LPP is a gap of 1.18x, 10LPP -> 8LPP is a gap of 1.11x, 10LPE -> 7LPP is a gap of 2x (8LPP -> 7LPP would be 1.53x gain), 7LPP -> 5LPE a gap of 1.25x, and 7LPP -> 3GAE a gap of 2x (1.6x gain vs 5LPE). All together 14LPP to 3GAE is a gain of 5.71x efficiency or a reduction in power of 82.5%.
TL;DR: Doing this math means that if 16FF+ is tied with 14LPP (which it is not), then 3GAE would be 8.8% ahead of N3E and 12-20% ahead of N3. Adjusting for the 1.32x difference in efficiency, puts N3E 21.3% ahead and N3 10-17.9% ahead. Samsung historically improves efficiency in their second iteration by about 10-20%, so 3GAP will likely be behind N3E and tied with N3. The rumors of 3GAP are probably wrong based on math, historical progression, and Samsung's failure to make an excellent FinFET node while GAAFETs are even more complex. If GAAFETs or Samsung's engineers turn out to be better than expected, it's possible that 3GAE and thus 3GAP are better than expected and can beat N3 class nodes.Reply
The GPU power isolation came from a friend of mine who analyzed the 3070 and and 2080. Both were minimally cut down variants of the 104 GPU of their generation. Using power virus loads he got 151 watts for the 3070 and 149 watts for the 2080.Reply
My friend was also the one who taught me the f^3.33 formula for estimating power differences from frequency changes. It’s pretty accurate across various GPUs. Unsure if this extends to all nodes when voltage and frequency scale well, or just FinFET nodes from Samsung and TSMC as my friend only demonstrated with FinFET GPUs. Reply
If Samsung didn't manage to make 3GAP outperform N3E they'd be in for some REAL trouble... Because it's comparing a GAAFET process to a FinFET process.
It will be a little bit better but it'll be *much* more expensive to manufacture (More process steps + Sammy yields). TSMC knows that, they wanted that to happen - they know that by sticking to an optimised FinFET design they'll very soon start pushing out much higher volumes of wafers that beats Sammy's GAA in Performance/$, they'll be raking in the cash while Sammy desperately tries to leapfrog them.Reply
Using Angstronomics' analysis of TSMC's N5's physical structures, we know it has a theoretical density of 137.6Mtr/mm2. The 171.3 number was N7 multiplied by TSMC's claimed improvement of 1.8x, but that was using an ancient Arm core that had a better implementation on N5 than N7. N3 would have a logic density of 233.9Mtr/mm2 and N3E would have a logic density of 220.2Mtr/mm2. N3P and N3X would have a further density gain of 4-8% over N3E at 229-237.8Mtr/mm2.
Intel 4 has a logic density of 122.8Mtr/mm2 as seen in the Angstronomics article. Intel 4 only has high-performance libraries and high-density libraries are around 40-50% denser. A hypothetical HD Intel 4 will have a theoretical density of 171.9-184.2Mtr/mm2. Intel 3 is a refined Intel 4 with HD libraries and further PPA improvements. I read somewhere that Intel 3 improves density by 18%, but can't remember where. Using this metric would give Intel 3 HP densities of 144.9Mtr/mm2 and Intel 3 HD densities of 202.9-217.4Mtr/mm2. Intel said that 7nm would be 2-2.4x denser than 10nm which is exactly where Intel 3 lands.
N5 HP has 0.671x the density of N5 HD and N7 has 0.7125x the density of N7 HD. N3E HP thus has a density of 146.8-157.3Mtr/mm2. N3P and N3X HP has a density of 152.6-169.8Mtr/mm2. Intel 4 thus is in between N4 and N3 class nodes in terms of density, with Intel 3 being a hair behind N3 class nodes. If yields are good this bodes well for the efficiency and performance of Intel 4 and Intel 3 allowing Intel to compete properly against AMD.
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Adonisds - Wednesday, April 26, 2023 - link
If N3B started volume manufacturing late 2022 why hasn't wasn't any product announced yet? Are all the N3B production lines idle and bleeding money? ReplyYojimbo - Wednesday, April 26, 2023 - link
I don't think they are idle at this point. They are working overtime but the yields are bad. They were likely idle in 2022, however. Why does TSMC say they started volume manufacturing of N3B in 2022? Because TSMC is always on schedule, even when they are a year late. Firstly, the only reason N3E exists is because the original N3 which they are calling N3B, didn't turn out as intended. As far as I know, only Apple is going to use it, later than they would have wanted, and only for the ultra high end of their product lineup. Rumor has it that TSMC is currently having trouble keeping up with Apple's demand for N3B even for the reduced A17 order. They are producing on it, it's just slow going. Perhaps one could say N3B was around to be available for "volume manufacturing" since late 2022 if one only wanted a small volume and was willing to pay a lot for it. N3B seems like a dead end with N3E set to replace it, supposedly with HVM in H2 2023. TSMC promised N3E HVM would begin 1 year after N3B HVM, and since apparently TSMC always keeps their promises we can't really trust that the H2 2023 situation for N3E will be any better than what the H2 2022 situation for N3B was, even though by now TSMC knows if anyone will actually be producing anything on the supposedly volume-ready node in H2 2023. ReplyTeslaDomination - Wednesday, April 26, 2023 - link
I wonder if this year's iPhone will be like the following:iPhone 15, 15 plus, 15 pro, 15 pro plus - A16
iPhone 15 ultra - A17 Reply
Adonisds - Thursday, April 27, 2023 - link
What happens while they are still working on yields? Do the use a reduced number of EUV machines and reallocate them to production lines of active nodes or do all the many N3B EUV machines stay idle in the N3B fab? ReplyYojimbo - Friday, April 28, 2023 - link
Just to avoid confusion, I want to stress that they don't directly need less machines because of bad yields. Bad yields means they need more capacity for the same number of good chips. But since Apple most likely originally intended to use N3B for the entire iPhone 15 lineup, they are likely looking at a reduced capacity demand for N3B.But to answer your question, I don't know. My guess would be they didn't have much idle for that long. They never built out the originally intended capacity for N3B because before it became necessary for them to do so they made the necessary decisions with their customers regarding intended usage of the node. TSMC are very good at managing their capacity. In the foundry business that's key to profitability. Reply
TeslaDomination - Wednesday, April 26, 2023 - link
If current rumors are to be believed, Samsung’s 3GAP outperforms N3 and N3E on the latest PDK. The only question now is the yield. I suspect N3E and 3GAP are in the 50% range. 30% for N3.I don’t think TSMC’s domination is a certainty at this moment, and I believe warren buffet’s decision to dump TSMC has less to do with China risks (Why didn’t he sell AAPL if China was a major risk) and more to do with Samsung. Reply
Otritus - Thursday, April 27, 2023 - link
Using the Apple A9 processor and Nvidia Pascal GPUs, we can estimate the performance-per-watt gap between Samsung's 14LPP and TSMC's 16FF+. I estimate the gap between the 2 to be at 1.3-1.35x, so I'll be using 1.32x for my calculations.The 1.32x figure can be demonstrated to be close to reality by comparing Nvidia's Ampere graphics cards to their Turing predecessors. By isolating the GPU core power, adjusting for frequency, and assuming a n% increase in transistors is a n% increase in power and no efficiency improvements from the Ampere architecture alone, we can determine Ampere to be 26.3% more efficient than Turing. Theoretically, 12FF to 8LPP would be a gain in 27.3% in efficiency. The power adjustment for frequency is based on the formula of f^3.33, wherein a 10% increase in frequency results in an increase in power of 37.4%. This is because the formula for dynamic power is power = cfv^2 (f is frequency and v is voltage) and voltage scaling isn't typically linear with frequency, but slightly above it. The f^3.33 is surprisingly accurate with a wide range of processors as long as they aren't falling off a voltage-frequency cliff.
16FF+ -> N7 is a gap of 2.5x, N7 to N5 is a gap of 1.43x, and N5 to N4P is a gap of 1.28x. Altogether, 16FF+ to N4P is a gain of 4.59x efficiency or a reduction in power of 78.16%. 16FF+ to N3 would be 4.76-5.1x efficiency (a decrease in power of 79-80.4%). 16FF+ to N3E would be 5.25x efficiency or a reduction in power of 80.96%.
14LPP -> 10LPE is a gap of 1.43x, 10LPE -> 10LPP is a gap of 1.18x, 10LPP -> 8LPP is a gap of 1.11x, 10LPE -> 7LPP is a gap of 2x (8LPP -> 7LPP would be 1.53x gain), 7LPP -> 5LPE a gap of 1.25x, and 7LPP -> 3GAE a gap of 2x (1.6x gain vs 5LPE). All together 14LPP to 3GAE is a gain of 5.71x efficiency or a reduction in power of 82.5%.
TL;DR: Doing this math means that if 16FF+ is tied with 14LPP (which it is not), then 3GAE would be 8.8% ahead of N3E and 12-20% ahead of N3. Adjusting for the 1.32x difference in efficiency, puts N3E 21.3% ahead and N3 10-17.9% ahead. Samsung historically improves efficiency in their second iteration by about 10-20%, so 3GAP will likely be behind N3E and tied with N3. The rumors of 3GAP are probably wrong based on math, historical progression, and Samsung's failure to make an excellent FinFET node while GAAFETs are even more complex. If GAAFETs or Samsung's engineers turn out to be better than expected, it's possible that 3GAE and thus 3GAP are better than expected and can beat N3 class nodes. Reply
Otritus - Thursday, April 27, 2023 - link
The GPU power isolation came from a friend of mine who analyzed the 3070 and and 2080. Both were minimally cut down variants of the 104 GPU of their generation. Using power virus loads he got 151 watts for the 3070 and 149 watts for the 2080. ReplyOtritus - Thursday, April 27, 2023 - link
This figure excludes vrm losses, memory, and other power like fans and lights. ReplyOtritus - Thursday, April 27, 2023 - link
My friend was also the one who taught me the f^3.33 formula for estimating power differences from frequency changes. It’s pretty accurate across various GPUs. Unsure if this extends to all nodes when voltage and frequency scale well, or just FinFET nodes from Samsung and TSMC as my friend only demonstrated with FinFET GPUs. ReplyWereweeb - Friday, April 28, 2023 - link
If Samsung didn't manage to make 3GAP outperform N3E they'd be in for some REAL trouble... Because it's comparing a GAAFET process to a FinFET process.It will be a little bit better but it'll be *much* more expensive to manufacture (More process steps + Sammy yields). TSMC knows that, they wanted that to happen - they know that by sticking to an optimised FinFET design they'll very soon start pushing out much higher volumes of wafers that beats Sammy's GAA in Performance/$, they'll be raking in the cash while Sammy desperately tries to leapfrog them. Reply
ballsystemlord - Thursday, April 27, 2023 - link
So who would use N3X exactly?AMD already has problems dissipating heat in their CPUs. You can't just add that much power without consequences. Reply
Otritus - Thursday, April 27, 2023 - link
Using Angstronomics' analysis of TSMC's N5's physical structures, we know it has a theoretical density of 137.6Mtr/mm2. The 171.3 number was N7 multiplied by TSMC's claimed improvement of 1.8x, but that was using an ancient Arm core that had a better implementation on N5 than N7. N3 would have a logic density of 233.9Mtr/mm2 and N3E would have a logic density of 220.2Mtr/mm2. N3P and N3X would have a further density gain of 4-8% over N3E at 229-237.8Mtr/mm2.Intel 4 has a logic density of 122.8Mtr/mm2 as seen in the Angstronomics article. Intel 4 only has high-performance libraries and high-density libraries are around 40-50% denser. A hypothetical HD Intel 4 will have a theoretical density of 171.9-184.2Mtr/mm2. Intel 3 is a refined Intel 4 with HD libraries and further PPA improvements. I read somewhere that Intel 3 improves density by 18%, but can't remember where. Using this metric would give Intel 3 HP densities of 144.9Mtr/mm2 and Intel 3 HD densities of 202.9-217.4Mtr/mm2. Intel said that 7nm would be 2-2.4x denser than 10nm which is exactly where Intel 3 lands.
N5 HP has 0.671x the density of N5 HD and N7 has 0.7125x the density of N7 HD. N3E HP thus has a density of 146.8-157.3Mtr/mm2. N3P and N3X HP has a density of 152.6-169.8Mtr/mm2. Intel 4 thus is in between N4 and N3 class nodes in terms of density, with Intel 3 being a hair behind N3 class nodes. If yields are good this bodes well for the efficiency and performance of Intel 4 and Intel 3 allowing Intel to compete properly against AMD.
https://www.angstronomics.com/p/the-truth-of-tsmc-... Reply